Hardware
Hardware
Hardware
Verification
Verification
Verification
Streamline your hardware production to reduce costs and accelerate the cycle.
Streamline your hardware production to reduce costs and accelerate the cycle.
Streamline your hardware production to reduce costs and accelerate the cycle.
Problem: hardware verification
Problem:
hardware verification
Hardware production cycle is expensive and long. Our architecture will scale it.
Hardware production cycle is expensive and long. Our architecture will scale it.
6-9 months production cycle for 1 chip design
Hundreds of engineers in verification team
6-9 months production cycle for 1 chip design
Hundreds of engineers in verification team
Our Product: Aleph Matrix for hardware
Our Product:
Aleph Matrix for hardware
Prove hardware properties from RTL and assertions
Prove hardware properties from RTL and assertions
Aleph Prover
Aleph Prover
is our state-of-the-art Formal Verification prover
is our state-of-the-art Formal Verification prover
Gesha
Gesha
is our Latent Reasoning Model
is our Latent Reasoning Model
Design + requirements
Verilog hardware designs, SystemVerilog assertions
Shared Lean models
Shared
Lean models
Express design behavior and properties as math
Checked proofs
Checked
proofs
Prove specific properties under stated assumptions
Aleph Prover + Gesha
AI-assisted reasoning for hardware verification
AI-assisted reasoning for hardware verification
Matrix fully integrates into existing workflows
Matrix fully integrates into existing workflows
We verify: one packet, one place, always.
A packet switch with stalling queues and gated clocks. Every accepted packet must be accounted for exactly once, from accept to delivery.
A packet switch with stalling queues and gated clocks. Every accepted packet must be accounted for exactly once, from accept to delivery.
Loss
Accepted, then nowhere.
Accepted, then nowhere.
Duplication
One packet, two places.
One packet, two places.
Phantom
Delivered, never accepted.
Delivered, never accepted.
Reset
Follows the declared spec.
Follows the declared spec.
Others feed the engine. Aleph Matrix finishes the proof.
Every accepted packet is accounted for exactly once: queued, in transit, or delivered.
Every accepted packet is accounted for exactly once: queued, in transit, or delivered.
What AI does
What AI does
Who closes it
Who closes it
When it stalls
When it stalls
Traditional FV 1
Traditional FV 1
Traditional FV 1
Agentic flow with HybridFV
Agentic flow with HybridFV
Agentic flow
with HybridFV
LLM drafts SVA, constraints and helper properties from spec + RTL.
LLM drafts SVA, constraints and helper properties from spec + RTL.
LLM drafts SVA, constraints and helper properties from spec + RTL.
Native engine only
Native engine only
Native engine only
× Escalates to a formal specialist
× Escalates to a formal specialist
× Escalates to a formal specialist
Traditional FV 2
Traditional FV 2
Traditional FV 2
Agentic flow with GenFV
Agentic flow with GenFV
Agentic flow
with GenFV
Agents run the loop: assertions, bind files, aux logic, refined on tool feedback.
Agents run the loop: assertions, bind files, aux logic, refined on tool feedback.
Agents run the loop: assertions, bind files, aux logic, refined on tool feedback.
Native engine only
Native engine only
Native engine only
× More helper properties; still bound by engine convergenece
× More helper properties; still bound by engine convergenece
× More helper properties; still bound by engine convergenece
Logical Intelligence
Logical Intelligence
Logical Intelligence
Aleph Matrix
Aleph Matrix
Aleph Matrix
Writes the proof: native local facts, global argument in Lean, tied to the exact assertion.
Writes the proof: native local facts, global argument in Lean, tied to the exact assertion.
Writes the proof: native local facts, global argument in Lean, tied to the exact assertion.
Native engine + checked mathematical proof.
Native engine + checked mathematical proof.
Native engine + checked mathematical proof.
A budgeted autonomous job: checked proof, bench-replayed defect, or explicit inconclusive.
A budgeted autonomous job: checked proof, bench-replayed defect, or explicit inconclusive.
A budgeted autonomous job: checked proof, bench-replayed defect, or explicit inconclusive.
Verifying a real RISC‑V CPU
Same pipeline, one open-source CPU, two questions
Same pipeline, one open-source CPU, two questions
Disproved
Disproved
Slower memory must not change what a program outputs.
Slower memory must not change what a program outputs.
Real race condition in the design: Fast memory → the CPU saves a corrupted return address.
Real race condition in the design: Fast memory → the CPU saves a corrupted return address.
Proved
Proved
On a system call, the CPU always jump to the handler within 36 clock cycles.
On a system call, the CPU always jump to the handler within 36 clock cycles.
Holds for a whole family of programs, from any starting state.
Holds for a whole family of programs, from any starting state.
The design
SERV, a small open-source RISC‑V CPU. Source modified.
SERV, a small open-source RISC‑V CPU. Source modified.
The questions
Written as assertions:
checks the spec must satisfy.
Written as assertions:
checks the spec must satisfy.
The answers
Proofs are expressed in a readable format for the customer's engineering team.
Proofs are expressed in a readable format for the customer's engineering team.
Checked by Lean
Every proof machine‑checked. No need to trust the AI.
Every proof machine‑checked. No need to trust the AI.
Hardware
Verification
Hardware
Verification
Hardware
Verification
Hardware
Verification
Streamline your hardware production to reduce costs and accelerate the cycle.
Streamline your hardware production to reduce costs and accelerate the cycle.
Streamline your hardware production to reduce costs and accelerate the cycle.
